Fabricating an integrated circuit (also referred to as IC, chip, or microchip) typically involves a plurality of processes. One development in semiconductor processing is the scaling of the integrated circuits to realize the smallest practicable feature size. Another driver in semiconductor industry is reducing the production costs. One way to reduce costs may be directly related with the number of required processes, wherein it is usually desired to use only as little number of processes as possible. Since errors or deviations from the optimally designed configuration may be introduced by the processes, due to misalignment, a limited overlay accuracy, inhomogeneities resulting from deposition processes and etch processes, a reduced number of processes may not only reduce the cost, it may also increase the yield, increase the reproducibility of the overall process, minimize the number of defective structural elements, and may reduce the time for the production of an electronic component.
In this regard, electrically contacting small structure elements (small meaning that the lateral extension of the structure element may be in the range of the according feature size of the planar processing) may cause problems if the size of the electrical contact is likewise small and the overlay accuracy of involved patterning processes may become relevant. Therefore, the electrically contacting of a structure element may be unreliable for structures, where the lateral extension of the structure element is not significantly larger than the electrical contact itself. According to this, additional processes are typically involved generating a larger contact landing area including one or more deposition processes, lithographic processes, etch processes (and the like) which may be undesired as described above, since the number of processes may increase.